Altera_Forum
Honored Contributor
17 years agoTimequest: Asynchronous feedback from output to input
Dear Forum,
I have some (may be too little) experience with Timequest, but now have a problem with an output register. That signal leaves the FPGA, goes through an aynchronous logic outside the FPGA and enters the FPGA as input and is clocked into an input register . How do I specify a constraint for that situation ? FPGA design is synchronous with one clock for input and output registers. Knowing that for example the maximum delay outside the FPGA is t_Extdelay, how do I specify a constraint saying that: tco(FPGA) + t_Extdelay(external) + tsu(FPGA) has to match the clock period. Many thank for an advice Best regards Juergen