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Altera_Forum
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18 years ago

The need for error correction codes

Hello, I'm working on digital design for the first time since college and I'm unclear on how much error correction is needed in FPGA/CPLD systems. Here's the situation: My design will s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Thanks to everyone for your help.

I've now added clock jitter to my timing simulations, changed my code to ensure that the state machine was detected by Quartus II, and forced the state machine to be "safe."

Hopefully that should cover all of my bases to the greatest degree possible.

Thanks again,

Jon