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Altera_Forum
Honored Contributor
Honored ContributorThe need for error correction codes
Hello, I'm working on digital design for the first time since college and I'm unclear on how much error correction is needed in FPGA/CPLD systems. Here's the situation: My design will s...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I should add that the "single event upsets" were my primary concern, but it looks like you guys consider this a very rare occurance. --- Quote End --- See http://www.altera.com/support/devices/reliability/seu/seu-index.html?gsa_pos=2&wt.oss_r=1&wt.oss=soft%20error%20rate.
