Forum Discussion
BQi
Occasional Contributor
Occasional Contributorthe link is invalid
https://www.intel.com/content/www/us/en/programmable/documentation/rso1586315108753.html?wapkw=Low%20Latency%20E-Tile%2040G%20Ethernet Pls help below link Low Latency E-Tile 40G Ethernet Intel FPGA...
CheepinC_altera
Regular Contributor
Regular ContributorHi,
As I understand it, in E-tile, we have Ethernet hard IP. To ensure we are on the same page, would you mind to further elaborate on the 40GE low latency MAC for E-Tile that you are referring to? If you are referring to a specific IP, probably some link to the IP in webpage would be helpful. You may also share with me the .ip file of the IP for better understand of the IP that you are using.
Thank you very much.
BQiOccasional Contributor
Occasional ContributorI don’t think it is the same document 40GE in H tile or E tile.
I can not find E tile in the document. And the update date is not correct,
This 40GE IP in E tile release in Apr.
