Targetting different FPGAs with NIOS II Design

Thanks for the reply LTS,

Interestingly although I am using only one PLL I decided to remove it so that the clock input pin is connected directly to the processor and I no longer see any errors - not holding my breath though as this being the solution.

With regard to generating the processor again, the problem with this is that the lwip changed from NIOSII 1.1 and when I create a new processor and come to compile the code in a later version of IDE I get errors concerning the read_phy_register command not existing. I have been on the nios forum, downloaded the lwip zip and installed it but still no joy. I will keep trying.