SystemC an alternative to Verilog??

systemverilog might be of high level abstraction, but systemc offers early software verification, where the system designers and software engineers can both use the same platform based hardware ip models.

systemC has a great scope to grow. Like, it has an advantage for software and hardware engineers to have a single common language. But this has many business issues, like the hardware ip vendors will have a much loss as their existing ips have their identities with vhdl or verilog.