Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSystemC an alternative to Verilog??
Hello, quick question for everyone. Are there any plans by Altera to permit SystemC in Quartus? I've been reading a lot of the benefits of SystemC and would like to try it out. Is SystemC an alternat...
Altera_ForumHonored Contributor
Honored ContributorI belive you are right , Systemverilog is a powerful language. I am fairly new to this business, but I have been using both SystemC and SystemVerilog and as I see it, there is no need for SystemC since Systemverilog offers a high level of abstraction and is well suited for simulation and verification. (And even synthesizeable :)).
But as i said, I am fairly new to this and I would appreciate inputs on my opinion. However, altera need to pick up the pace finish the quartus support for systemveilog.
