SystemC an alternative to Verilog??

If you've been reading a lot about SystemC then you may have noticed that the focus of this language (if you call it a language at all) is high level simulation and verification. Synthesis also can be done with it but at the cost of some overhead compared to Verilog and VHDL. Because of that, I assume that FPGA vendors will not adopt SystemC. To my knowledge, Mentor ModelSim does support SystemC and Verilog/VHDL co-simulation.