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Altera_Forum
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15 years ago

Synchronous Design Timing (VHDL)

Hi All, I am very new to VHDL and working with hardware so I'm hoping this forum can fill in some of the giant holes in my knowledge. My current question relates to timing in synchronous d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Here are the two diagrams I think you are seeing - is the first one what you see in modelsim?

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Yes, in ModelSim everything looks instantaneous, but you're right that it's behaving as if it's not (like your 2nd picture) - which is good!

Thanks!