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Altera_Forum
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15 years ago

Synchronous Design Timing (VHDL)

Hi All, I am very new to VHDL and working with hardware so I'm hoping this forum can fill in some of the giant holes in my knowledge. My current question relates to timing in synchronous d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Now that you have had a play with the components, go back and read the FIFO megacore users guide.

There are two FIFO read-modes; legacy mode and show-ahead mode. In legacy mode, rdreq acts as a read-request, with data changing in the clock after its asserted. In show-ahead mode, the signal is a read-acknowledge.

Try both modes so that you can understand the slight difference in timing of the data at the FIFO output.

Cheers,

Dave