Synchronous Design Timing (VHDL)

Implement your logic to operate on the rising-edge of the clock.

The FIFO Megafunction guide comes with some examples.

Learn how to use the Modelsim simulator, and write a testbench to test your logic. If you are not sure how to write a testbench. Explain to me what you want to do with the FIFO. I have some FIFO testbenches that I can modify to show you how they work.

This testbench would be used with Modelsim, and would be in VHDL, so you can use the Altera-Edition. Download it and go through the Modelsim tutorials if you have never used it before.

Cheers,

Dave