Forum Discussion
Steve89
New Contributor
New ContributorSync Resets with Clock Enables
With AMD FPGAs, sync resets are recommended. Coding in HDL is straightforward because the sync reset input has priority over the clock enable. Intel FPGAs have a different priority. Async resets, ...
ShengN_altera
Super Contributor
Super ContributorHi,
Sync reset is more recommended compared to async reset in terms of retiming.
In terms of logic, sync reset with clock enable will have more logic compared to sync reset (screenshot):
Async reset with clock enable have same logic as async reset (screenshot):
Thanks,
Best Regards,
Sheng
