Support for floating point arithmetic and the VHDL-2008's float_pkg by Quartus-II

I wonder, if there's a reasonable way to implement pipelining in a behavioral description like IEEE.float_package. It must use explicite register instances that can't be hidden in a function or operator.

As discussed previously, the Quartus synthesis has capabilties to "pull" register instances into an inferred integer divider, but the registers still need to be defined besides the "/" operator. Bu this looks like a good way for a float package implementation.