Suggestions for simple link between two FPGAs?

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I said 10 MByte/sec, not 10 Mbit/sec, so my skew margin is 5nsec

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My mistake, I meant to say 5, not 50. Anyway 5ns mismatch is a foot or two of cable propagation delay equivalent differential length at a reasonable impedance.

It would be hard to get signals anywhere nearly that badly mismatched in time relative to each other coming from the same small physical source over a foot or so of transmission distance using any kind of proper impedance control / termination. It shouldn't be an issue to get 100Mbit/s, and if you're worried about it you can use two data lanes at half rate instead of one, but I'd just design the interconnect properly and not worry about it.

LVDS gets used more than for that sort of speed and distance all the time.