StratixI maximum input current

I told a reasoning why I opt for 25 mA (continuous) clamping current. There's a possibility that I underrate the FPGA ruggedness in this point, better than overrate. Dynamic output currents can be considerably higher than -25/+40 mA.

I understand that your overvoltage problem is related to continuous input current.

Another possible source of information is the Stratix Ibis file, it shows all kinds of pin V/I characteristics, including clamping operation.

I still wonder how you can be sure that the FPGA is correctly configured when the supply short happens.