Stratix10MX, triple speed ethernet LVDS IO

Hi dlim,

1) I found a limit of 14 TSE IPs. After this number, the fitter could not find a suitable scheme for pin assignements. (it seems you can drive only 1 PLL per bank, i think i read this limitation somewhere in a datasheet )

I sent you the .qar file of my early design with 15 TSE LVDS IO.

2) There is no design example provided with S10 soc kit which instanciates a TSE IP with LVDS IO. However, you can see in golden_top design (see the attached qar) that sgmii pins are linked to gxb transceivers. Those ones may be used with a 1G/10G phy design but there is no example which explicitly shows how it has been implemented.

Maybe, you can tell me more about this.

Thank you,

Have a nice day,

regards,

John