Stratix10MX, triple speed ethernet LVDS IO

Hi,

Thank you for your reply.

i am using the 1SM21BHU2F53ES2 for test purposes (Stratix 10 MX FPGA Development Kit). I didn't assign any IOs at first as the planner can do it automatically.

see the error i get during plan stage :

I was asking about the Tile transceivers because i downloaded an example design from INTEL (Stratix 10 SoC fpga devkit, schematic p.13) where IOs for the triple speed Ethernet were connected to dedicated transceivers(GXBR4M_RX_CH4P, GXBR4M_REFCLK4P for example).

Thank your very much dlim

Best regards,

john