Hi John,
For a start, unfortunately TSE IP is designed to interact with LVDS IO only in Stratix 10 FPGA. Therefore, you can't connect TSE IP to H-tile or L-tile.
I am not sure exactly which Stratix 10 MX OPN that you are using nor what's the fitter compilation error that you saw, but the easiest way to debug fitter error is to disable all FPGA pin location assignment and let Quartus to try auto fit the design.
Another thing that you can check is to look at the fitter summary report for your 8 TSE design. From there, you would be able to tell how many LVDS IO and IOPLL has been consumed vs available IO and PLL resource. After that, you can calculate and estimate the required resource for 16 TSE design.
Thanks.
Regards,
dlim
Occasional Contributor
