Stratix V timing constraints?

Hi,

I am trying to read data from a simple 8 channel 12 bit ADC using a Stratix V Gx dev kit.

Bitclock 480MHz

Frame Clock 80MHz

I try using source synchronous PLL megafunction for the bitclock and use the DDIO megafunction for reading the data.

But I can't meet timing.

I have checked rd07222013_432 (http://www.altera.com/support/kdb/solutions/rd07222013_432.html)solution already. But this patch doesn't fix my timing.

If i try the same PLL/DDIO on a stratix IV gx dev kit, I can meet timing constraints. But the Stratix V fails..

Is there something quirky with the Stratix V?

I'm guessing if simple DDIO doesn't work, ethernet/ddr3/pci express are a long shot..

Anybody else in the same boat as me?

I have submitted a service request.. Lets see.

Thanks

ZubairLK