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Honored Contributor
Honored ContributorStratix IV Hold Violations....
... between register A and B. Both Registers are fed by a Global Clock. Source Register and Latch Register are in adjacent labs. The problem seems to be coming from Register A being of type "ALM R...
Altera_ForumHonored Contributor
Honored ContributorHow many LUT_REGs are being created? Open the Fitter Report -> Resource Section and it should be the ~4th row. These are created as a matter of last resort, when running out of regular registers, so most designs have 0.
They are slower registers since they're made from LUTs, and have larger micro setup/hold times. That being said, there shouldn't be that many, and the router does not have to add much delay to meet the hold requirements, so I'm really surprised enabling hold timing is causing this. Are you sure nothing else is creating positive hold requirements in the design?
