Stratix IV GX transceiver transmit simulation

Hello,

I am trying to simulate (with Mentor Questa) the transmit part of a Stratix IV GX transceiver.

I defined the protocol as basic and I disabled the 8b10b part.

Whatever I set on the txdatain port, I get the tx signal of the transceiver toggling in the same sequence. I get a sequence is: 1111011000111101100 (that could look like a K.28.6 in 8b10b)

I want to use the transmitter to generate a high speed signal without any protocol. (I don't want/need clock recovery on the receiver side). So I just want the value on txdatain to be serialized.

Transceiver vhdl file is attached.

Did any run a simulation successfully in such a setup?

Thanks,

raph

Here is my mapping:

Trans_inst : Trans port map (

cal_blk_clk => Clock_125,

pll_inclk => Clock_125,

reconfig_clk => '0',

reconfig_togxb => "0000",

rx_coreclk => Clock_125_bus,

rx_cruclk => Clock_125_bus,

rx_datain => dataline,

rx_locktodata => "00",

rx_locktorefclk => "11",

tx_coreclk => Clock_125_bus,

tx_datain => "1111111111111111111111111111111111111111",

reconfig_fromgxb => open,

rx_clkout => open,

rx_dataout => open,

tx_clkout => open,

tx_dataout => dataline);

PS2: I get the following message while simulation, I doubt it is related:

# ** Warning: (vsim-8683) Uninitialized out port /tb/Sata_trans_inst/Sata_trans_alt4gxb_component/cal_blk0/nonusertocmu has no driver.

# This port will contribute value (U) to the signal network.

# ** Warning: (vsim-8684) No drivers exist on out port /tb/Sata_trans_inst/Sata_trans_alt4gxb_component/ch_clk_div0/dprioout(99 downto 94), and its initial value is not used.

# Therefore, simulation behavior may occur that is not in compliance with

# the VHDL standard as the initial values come from the base signal /tb/Sata_trans_inst/Sata_trans_alt4gxb_component/wire_ch_clk_div0_dprioout(99 downto 94).