Stratix IV GX dev kit

Dave,

I just want to use the 16 channels as serializers: output 16 parallel arbitrary sequences of bits that will be stored in memory in the FPGA. There will be no receiver, and there is no protocol involved. It is just a serializer. This will be used to test a piece of equipment that I have.

The reason to use transceivers is that I need to have the ability of precisely align the edges of the 16 channels (in the subnanosecond range), and for that I need the very high frequency clock that the transceivers provide. Those edges have also to be sinchronized between them (if two transitions should happen at the same time, they cannot happen 1 ns apart). I understand that there is no output feedback / pll that guarantees that they will be synchronized, but hopefully there will be minimal variation between channels if they are all locked to the same clock (I hope in the low picosecond range). That obviously depends on how the internal hardware design, but I would expect them to be almost identical.

Does that make sense?

I am sorry if I am not been able to clearly explain what I want to do; it is really very simple but I find it hard to write it down.

Thanks,

Miguel