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Honored Contributor
Honored Contributorstratix III with DDR2 temination
hi my design include stratix III device with 2 ddr2 hp core. each core is facing 5 DDR2 components when 1 of the 5 is for ECC. i looked at the termination schemes in AN408 and not found my ans...
Altera_ForumHonored Contributor
Honored Contributordata lane : 16 DQ + LDM +UDM +UDQS + LDQS = 20 * 10 = 200
running on 150Mhz clk => 300 Mhz data rate
