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Altera_Forum
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13 years ago

Stratix III reconfigurable PLL switched clocks

Hello! I'm having some strange troubles with a reconfigurable PLL. I have to write my settings to c2 to configure c1 and vice versa. The baseclock is 5.25MHz. The M multiplier is 199 (100 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Setting the option "Preserve PLL Counter Order logic" solved the problem. I must have overlooked this.