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Altera_Forum's avatar
Altera_Forum
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17 years ago

Stratix III JTAG Failure

Hi All,

I have problem on Stratix III device on my Custom development board.

Device: Stratix III - EP3SL340

Download cable : Altera USB Blaster

We have provided two configuration option to configure the FPGA (JTAG & Passive serial).

Only one device is connected with the JTAG interface.

We are frequently using JTAG & USB blaster interface to validate our designs. so far It was working nicely.

Suddenly the quartus Tool is not able to detect the device from the JTAG chain.

I just went through the JTAG troble shooter, It gives the information of possible failure in the JTAG interface signal,

Also I have noticed that TDI pin is almost shorting to GND.

It shows 2 Ohm between TDI to GND.

Whereas the other working board it was around 150 to 200 ohm.

This is the second board I am facing the same issue.

Is it the problem with the Stratix III device JTAG interface.

Can anyone help me to findout the root cause for this trouble.

Best Regards,

Kalidoss

22 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The first step in debugging JTAG issues is always the same. Grab an oscilloscope and take a look at the JTAG signals.

    I would say the low impedance to ground is obviously a good first place to look.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Jack,

    Got the Scope & probed the JTAG TDI,TMS, TCK, TDO signals.

    I could able to see TDI, TMS are toggling from 0 to 3.3V level.

    But TCK is not toggling it is hardly singing from 0V to 0.3V. (Inityially I mentioned the signal name wrongly as TDI). This TCK net is showing 2 Ohms to GND.

    This is the reason the JTAG chain is not able to detecting the device.

    Also I have tested with other boards & TCK is toggling from 0v to 3.3V.

    How to rectify this problem.

    I Have the JTAG header which is directly connected to the FPGA.

    For your reference I have attached the JTAG interface section of Stratix-III FPGA wth this message.

    Expecting your valuable suggestion over here.

    Best Reagrds,

    Kalidoss
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    First I would measure that 1K resistor to ground and make sure it's really 1K. If that's not the problem it really sounds like you've got a solder short somewhere. There are tools out there that can pinpoint where a short is (simply by measuring resistance to a very large number of significant digits). For example, try measuring the resistance to ground both at the JTAG header and at the via where it connects to the FPGA.

    What is your relationship like with the assembly house? We often have the assembly house x-ray the board when something like this happens. If this is happening consistently, it points to an assembly problem (too much solder paste, too much solder).

    It could possibly be a layout problem. What tool did you use for layout? Is there anywhere in the layout where you could see a danger of TCK shorting to ground.

    Is this a lead-free board?

    Have you done any rework on the board? I've often seen people leave flux on the board after doing rework, then they power up the board and it works for a while until the solder heats up under a BGA and the flux residue makes it flow.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Jack,

    FYI --> This board was working fine for quite long time. Suddenly JTAG interface is not able to detect the Device.

    Measured the 1K resistor is value & it is fine.Also measeured the impedance from connector as well fom FPGA TCK pin It shows 2 ohm.

    I am not in position to suspect LAYOUT, Since enough spacing(200mil) is provided for TCK signal. we are using Allegro for our LAYOUT. Infact all other boards are working fine.

    It is not a lead free board. Components are leadfree & but assembled with leaded profile.

    Kalidoss
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi Jack,

    For your reference I am attacheding the TMS & TDI input waveform captured as part of JTAG debugging. TDI & TMS is togglingfrom 0v to 3.3V. But TCK is not toggling. It stays remains at 0V. Looks like it is getting loaded beause of this low impedance(2 Ohm)

    Kalidoss
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    TCK is not toggling

    --- Quote End ---

    --- Quote Start ---

    TCK net is showing 2 Ohms to GND

    --- Quote End ---

    Can be regarded as synonymous, I think. There's nothing to measure except locating the short. You should be able to detect by voltage drop method, if it's near the FPGA or the JTAG connector. Unfortunately, it's difficult to clearly distinguish FPGA internal from external PCB short near the FPGA without desoldering the device or using x-ray. Possibly, an FPGA internal short reveals by a voltage drop at FPGA supply pins when soucing a current to TCK.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi FvM,

    Infact I have removed the connector & measured the impedance between TCK to GND. It remains 2ohm between TCK to GND..

    Also I am maintaining 3W spacing in the layout for TCK from other net. The closest net is TDO which is 18 mil away from this TCK.

    For your reference I have attached the bmp file which will shows the TCK routing on my board.

    I am suspect something happened to the internal buffer of the FPGA.

    Is there anyway to find out the internal buffer shortage. Isolated the
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I think you're stuck. Can you have the board X-rayed? If it's inside the FPGA, I don't see any method for debugging (other than removing the part). Obviously you can't use boundary scan to test the TCK pin. If it is inside the part, is there any circumstance you can think of that might have caused damage? (Could have even been ESD).

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The 2 ohms residual resistance seems to indicate an FPGA internal damage rather than a simple PCB short, that can be expected to show zero ohm.

    There's a point in your post that seems dubious to me, although it's most likely unrelated to the discussed TCK pin failure.

    --- Quote Start ---

    It is not a lead free board. Components are leadfree & but assembled with leaded profile.

    --- Quote End ---

    No chip vendor (also Altera) doesn't support processing of lead-free BGA packages with leaded solder paste. This option exists for all other package types, except such with BGA balls. The resulting non-eutectic alloy won't give reliable solder joints.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi FvM,

    You are right, No body supports this type of soldering profile.

    But our ODM team have done many leadfree parts with leaded assembly prfoile. So far we have seen the good result from their assembly.

    Also would like to know is there any way to debug this TCK issue apart from removal of the FPGA.

    Because I am able to program the FPGA by using PS configuration & it is working fine.

    Best Regards,

    Kalidoss