Stratix III Dedicated clock or not dedicated ?

Starting a design with 32 LVDS input data (I'm planning to use OCT Rd) and 32 LVDS output data @250MHz, I'm wondering which kind of clock input I should use:

-CLK[1,3,8,10] are dedicated "high-speed" clock input pins that do not support OCT Rd (whereas they are labeled "High-Speed", rather strange isn't ?)

-CLK[0,2,9,11] are I/O or clock input pins that seems to be dedicated to the SERDES blocks (documentation not very clear) and that support OCT Rd.

-CLK[4..7,12..15] are I/O or clock input pins that do not support OCT Rd.

Does anyone know what's the difference between "high-speed" clocks, SERDES dedicated clocks and other clock inputs ?

More over, knowing that, though my current design don't need the SERDES, I'd like to experiment the SERDES/DPA capability later with the same board, which clock input pins should I prefer ??

Thanks