Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Stratix II PLL and crossing clock domains

Hi, I want to transfer data between two clock domains(12 MHz to 20 MHz). I am using a Stratix II FPGA PLL to generate both clocks from a 100 MHz clock. I need that the first rising...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I don't understand from your post, which kind of data transmission is intended. At first view, it look like a parallel transmission, as jakobjones expects, when suggesting a FIFO.

This sentence however seems to indicate a serial transmission:

--- Quote Start ---

The input data length is 48 and the output data length is 80, so time duration of both frames is 4 us.

--- Quote End ---

In this case, simply the common 4 MHz clock could be used as a frame sync., generated from the PLL together with 12 and 20 MHzl.

Apart from these considerations, that try to utilize the integer clock ratio, they can be simple treated as unrelated, using common cross domain transfer techniques.