Honored ContributorHi,
I am working with the PCI Express Development Kit, Stratix II GX EP2SGX90F1508C3. I am trying configure to download a .sof file in this FPGA but one error occurs: Can´t access JTAG chain. I am using the FPGA alone, it doesn´t coupled to the PCI. Does somebody know the cause of this error?
Honored ContributorDid you close the HSMCA_JTAG and HSMCB_JTAG bypass switches as documented in the manual?
Honored ContributorNo, I didn't. How can I do this? I don´t found the Configuration DIP Switch in the PCI Express Development Board, only the User DIP Switch.
Honored ContributorGood question! The configurations switch is documented in the reference manual but not detectable in the very detailed layout photo Fig. 2-2. It's a kind of mystery, but as I don't have the board, I can't reveal it. I think however, that even without a consistent documentation, you should be able to find out if the JTAG chain ist actually continued or broken at the HSMC connectors, as suggested by the manual. And you could help Altera support to fix the reference manual.
Honored ContributorI think that I was connecting incorrectly the USB Blaster in the board. Now, it is occurring the following error:Error: Device chain in Chain Description File does not match physical device chain -- expected 1 device(s) but found 2 device(s).
Does somebody know why this error occurs?Honored ContributorTwo devices in JTAG chain should be expected, you have the MAX II configuration controller and the Stratix II FPGA. The error is only in not scanning the JTAG chain before assigning the programmer action, I think.
Honored ContributorI think the MAX II device on the Stratix II GX PCIe board has a special build of the PFL that requires you to push one of the buttons on the board to get programming stuff to work. There's some documentation in the PCIe-to-DDR example project that talks about programming the on-board flash. I believe it talks about having to push a button to get the MAX II's PFL to talk to the Quartus programmer.
