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Altera_Forum's avatar
Altera_Forum
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13 years ago

stratix 3 fpga interface with ethernet

Hello sir,

I am designing a hardware board for general purpose in which FPGA has to interface with ethernet . Can u please tell which ethernet has to be taken and on what basis? and also tell about the connection.

Thank you

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    You will need an external PHY to make the interface between the Ethernet port and the FPGA, and an Ethernet IP inside the FPGA, such as Altera's TSE or Opencore's Ethernet MAC.

    The first thing you need to decide is whether you require a 100Mb/s or a 1Gb/s interface. Then from that choose a PHY, see how you can connect it to the FPGA and choose a MAC.
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    Altera_Forum
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    ok sir thank you.100mb/s is sufficient for my application. Can you please tell about schematic of this interfacing.

  • Altera_Forum's avatar
    Altera_Forum
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    I don't have any finished design to show you, but you can have a look at some PHY datasheets for suggestions. In my company we use PHYs from SMSC and we are quite happy with them:

    http://www.smsc.com/products/ethernet_and_embedded_networking/ethernet_transceivers/lan8710a_lan8720a

    You will find a lot of information in the datasheet itself, and you can also find in the download section some schematics for an evaluation board.

    For the FPGA side I suggest reading the TSE documentation: http://www.altera.com/literature/ug/ug_ethernet.pdf.
  • Altera_Forum's avatar
    Altera_Forum
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    Sir,

    We are using STRATIX 3 FPGA(EP3SL340F1152) in our design.

    We are providing ethernet interface on our board in order to increase the communication speed compared to RS232.

    Can you please tell us which ethernet can be used?
  • Altera_Forum's avatar
    Altera_Forum
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    You decide which Ethernet interface you need. Then from that you select a PHY, and then you look at how you want to connect it to your FPGA. Different PHYs with different Ethernet protocols supports have different interfaces to the MAC, using more or less pins. The more pins you use, the lower the frequency and the easier it is to interface with the FPGA, usually.