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Yes at most the DMA will transfer one world per clock cycle, so yes there is something strange.
What DMA did you use? Some DMAs have a limit on the number of words they can transfer. Are you sure that all 2Mb were actually transferred?
Are you sure that you wait until the DMA transfer is finished before triggering the performance timer? If set in asynchronous mode, the function that starts the DMA transfer will return before the transfer is actually complete.
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Thanks for the input. I am using the DMA core from Qsys, not the SGDMA. The maximum transfer size in byte allowed by the DMA is 2^32. So I think 2MB is not over that limit.
I cleared the data in SRAM before transfer data into it. Through step by step debug, I could see from the memory monitor that the data in SRAM was refreshed by the newer value, and I also have a comparison function to compare the result.
As for the performance core, I started it before I post the transmit and receive request, and stopped it after the receiver set a bit saying the data has been received. I also set up an output test port with the same start and stop time and monitored it with an oscilloscope. And the results of the performance core and the oscilloscope met with each other...
The only thing I can think of is the asynchronous mode you mentioned. But I didn't find related information in the description of DMA... How can I verify this?
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