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Altera_Forum
Honored Contributor
Honored Contributorstrange behaviour of square root VHDL code
I need a plain VHDL-square root code for a special purpose and used "google code search". I thus found the following code in their files, obviously written by Altera. http://www.google.com/c...
Altera_ForumHonored Contributor
Honored Contributorallthough the code works, I'd like to return to this. Can it be that I interpret the code in a wrong way? What are the higher bits intended to indicate? Is it only a sign?
I is because I see, that some bits are suppressed during code synthesis.:confused:
