strange behaviour of square root VHDL code

Thanks very much so far. The above mentioned code seems to be similar, I will investigate this. :)

In the meanwhile, I am correcting the error manually. It is tricky because of the delay but works: I am just switching the outut appropriately.

I really would like to understand, where this comes from. It is only the Bit N-1 causing an inverted calculation. I think there is somehow an overflow with the signed/unsigned during one of the substractions, causing parts of the algorithm to work in the "wrong direction". I tried to change the bits intuitively to find the reason, but was not able to figure it out, however.

A big german beer at the forthcoming octoberfest in munich is waiting for the man, explaining me this issue :-)