Sorting in FPGA

In 2006 I spent a couple of evenings to do a median of up to 9 elements. It comes down to what Dave says: you compare every element to every other element and you tally the comparisons for every element. The element whose tally equals the median index is the result. I did the work in AHDL, so it is fairly cumbersome to expand to 25 elements. Comparing only the 4 upper bits for 9 elements uses 287 LC in a Stratix EP1S25 and fully pipelined (3 stages) achieves 175 MHz. I estimate 25 elements to use about 2400 LC : ((e * (e - 1)) / 2 ) * (cw * 2)