Sorting in FPGA

If the calculation time is not a priority, then I would go for brute force simplicity;

1. Create a design containing;

- median value register

- median count register

- current value register

- current count register

2. Create a control FSM that;

a) Loads the 'current value' register with the first value in RAM

b) Loops over all RAM locations, incrementing the 'current count' register when the RAM value matches the 'current value' register

c) At the end of RAM, compare the 'current count' with the 'median count', and if 'current count' is greater, load the median registers from the current registers.

d) Repeat for all RAM locations.

At the end of this loop, the median registers will contain the median value and the number of times it occurs.

Cheers,

Dave