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I think you need the frame buffer because of the synchronization problems you might have with DVI throughout , am I correct ?
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yes, correct. as jakobjones mentioned, you will need to add framebuffer before clocked video output.
so, if you want to put your dummy passthrough component , then you can place it between clocked video input and framebuffer.
you will need to refer the verilog hdl books for the basics, i think. just giving a simple example of a pass through component for you to start with.
module dummy_module(clk, reset, data_in, data_out);
input [7:0]data_in;
input clk;
input reset;
output [7:0] data_out;
assign data_out = data_in;
endmodule
here add the necessary signals like you mentioned (clk, reset, data, valid , ready. etc). you can start with simple modules to get better understanding about the data types and signal connection and stuff. good luck!
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