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Honored Contributor
Honored ContributorSopc Help
hi again, I'm using a SDRAM controller in SOPC. but things are not working right. Failing paths, buffer of templates are getting full , ... I'm using master write and master read ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You have to enable the settings for that? Cauze i can't find it in the main directory. --- Quote End --- AFAIK sopc builder generates the sdc file by default, together with the .qip file which contains the hdl file references. At least this is true for the Quartus version 9.0sp2 I use. Did you select TimeQuest as time analyzer? Regarding the sdram clock phase, I remember it must be calculated somehow like this (although I'm not completely sure): - pre-compile the project with 0 phase shift - search the PLL offset in the timing analysis report - search the sdram clock combinatorial delay from pll output to clock pin - the sdram clock phase lead must be set that the sum of pll offset and combinatorial delay is a bit longer than the sdram setup time - recompile the Quartus project I use the same SDRAM as yours and EP3C40: with Fclk=100MHz I set dram clk phase = -27degrees = -0.75ns. As a rule of thumb you can also try -0.75ns which for your 148MHz would mean a phase lead of 40deg. Regards
