Sopc Help

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Either you are using a too high clk frequency

or you have a bad create_clock command in the TimeQuest sdc file.

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Fmax is about 132MHz but that is when i remove all the others VHDL and only generate a Sopc with one Write master and one SDRAM controller.

The second option could be a problem. I don't have much experience with

SDC file or asserting constraints. I followed TimeQuest User Guide by Ryan Scoville. do i need a diffrent ip.sdc for the sopc? Here is my SDC-File for main design:

# **************************************************************#  Time Information# **************************************************************
set_time_format -unit ns -decimal_places 3
 # **************************************************************#  Create Clock# **************************************************************
create_clock -name {FPGA_CLK1} -period 20.833 -waveform { 0.000 10.416 } 
create_clock -name {FPGA_CLK2} -period 20.833 -waveform { 0.000 10.416 } 
create_clock -name {PIX_CLK} -period 20.833 -waveform { 0.000 10.416 } 
 # **************************************************************#  Create Generated Clock# **************************************************************
derive_pll_clocks
 # **************************************************************#  Set Clock Latency# **************************************************************
 # **************************************************************#  Set Clock Uncertainty# **************************************************************
derive_clock_uncertainty

FPGA_CLK_1 and _2 are 48MHz input clk's that go straight to a PLL each. They generate a freq of 48MHz and 144MHz.

The generated CLK 144MHz i use for the SOPC gives failing paths (setup)

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Some suggestions:

- If the SDRAM controller you are using does not support burst then don't enable bursting in the masters.

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It does. It supports a burst of 1,2,4,8. I set every burst on 8.

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- Increase the arbitration share of each master to allow multiple back to back transfers from each master to access the SDRAM

- Increase the data width of the master to match your memory controller width

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I'll try them, but i was trying to avoid the last suggestion because then i need to make the code a little more complex.

If i increase arbitration shares, that will have no affect on the slack.

or am i wrong?

Aditional info:

FPGA : Cyclone III EP3C10F256C8N

SDRAM : IS42S16400B

If more info is required plz ask.

Thx for the reply's.