sopc clock bridge time slack

hi,

In my sopc system ,there are several masters to access ddr2 ，the clk of ddr2 is150MHz at full rate ,and 100MHz of cpu and dma mater.so connected system is like that i connect ddr2 to clock bridge master port, and connect cpu and dma master to clock bridge slave port .but after compiling ,there are time slacks on cpu ,dma and bridge path .In the setting of clock bridge ,there is a choice of slave domain synchronizer length and master domain synchronizer length, the ip datasheet suggest that it is determined by TimeQuest timing analysis , i don't know how to select by timerequst. and i don't understand the explaining of increasing this value leads to a larger meantime between failures (MTBF) in the datasheet?

are there any method to improve sopc time?

any good suggestion, thank first!