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Altera_Forum
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14 years ago

SOPC based PCIe design issue

Hi

I was building an SOPC based design with PCIe as a component. I instantiated the design and enabled the required clocks. After downloading the design, when i restart the computer, the computer switches OFF before starting again. I am using a DE4 board for the design. The PCIe demo provided by Terasic works fine. Any pointers as to any signals i might be missing.

The following are the signals that i have instantiated particular to pcie.

.cal_blk_clk_0(enet_refclk_50MHz),

.busy_altgxb_reconfig_pcie_compiler_0 (busy),

.fixedclk_serdes_pcie_compiler_0 (enet_refclk_125MHz),

.gxb_powerdown_pcie_compiler_0({~PCIE_PREST_n}),

.pcie_rstn_pcie_compiler_0(PCIE_PREST_n),

.pll_powerdown_pcie_compiler_0({~PCIE_PREST_n}),

.reconfig_fromgxb_pcie_compiler_0(reconfig_fromgxb),

.reconfig_togxb_pcie_compiler_0(reconfig_togxb),

.refclk_pcie_compiler_0(PCIE_REFCLK_p),

.rx_in0_pcie_compiler_0(PCIE_RX_p),

.test_in_pcie_compiler_0(test_in),

.test_out_pcie_compiler_0(test_out),

.tx_out0_pcie_compiler_0(PCIE_TX_p),

.reconfig_clk_pcie_compiler_0(enet_refclk_50MHz),

I have instantiated a altgx_reconfig core with offset_cancellation_reset input for generating the busy signal. The signal tap shows all the clocks running properly. Any idea as to why the issue might be happening.

Thanks & Regards

Hari

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Harikris,

    Your clock setup is okay. Stay with Gen1 for now. I recommend using x1 to start with. Which clock are you using from DE4 board? I'm using "gclkin" (100MHz) from schematic page 6. Use this as your free running clock. Make sure you set SW7 switch for 100MHz. Use this clock to generate 50MHz and 125MHz for your system. I hope this helps.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Kattice,

    Could please tell about the altgx_reconfig instance that you used. Which all signals did you enable for this instance.

    Regards

    Hari
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Kattice & nekojiru,

    I got the issue solved. It was due to the PCIe(x16) slot itself. I changed to another x8 slot and my designs are working fine. Never tried to check this before since PCIe Fundamental demo was working fine.

    Thanks & Regards

    Hari
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Glad to hear that it's working. Are you using x4 or x8? I noticed also that CPU or chipset do make difference how they are trained up. I'm having issue with IP timing issues when I use x8 lane. Do you have timing issues?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I used both Gen1 and Gen2 x1 configurations. I am using the MM signals to just write to some registers for now. Did not get any timing issues. I will try x4 or x8 and reply back.

    Regards

    Hari