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Altera_Forum's avatar
Altera_Forum
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15 years ago

SOPC and beginbursttransfer

I am creating a custom Avalon MM Master that will need to speak to a HPCII DDR2 controller. Rather than generating the core in the SOPC tool, we are generating it using the Megawizard in Quartus. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You would need a burst counter too since you could have two back to back bursts and so there is no edge to detect. So you could have something like (burst_counter == 0) & (read | write) and then do an edge detect on that assuming that the counter being 0 is when it's ready for a new burst. This signal doesn't heed waitrequest, so if the local_ready is low when burst begin is high you don't continue to hold burst begin high like you would with say read or write.

Alternatively you could just make a bridging component where the slave port is in the system and you expose all the wires to the top level with a conduit. One of the slave lines could be the burstbegin signal and the fabric will drive it for you. This all assume that this signal still works.... I have no clue since I have always avoided using it.