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Altera_Forum
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12 years ago

Some problem about CPLD EPM570

Hello, I have some problems about EPM570. What's the GCLK maximum value that could be accepted? I searched datasheet and found it can input higher than 100 MHz. But I input a 100 MHz XTAL and C...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Don't know what you mean with "detect I/O pin"?

Besides correct waveform of the clock oscillator signal (voltage level, rise/fall times, clean edges), timing analysis should verify that the design can run at 100 MHz.