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Altera_Forum
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17 years ago

Some glitches in the simualtion waveforms

Hi, Experts, I met a problem in my VHDL code. My algorithm is to cut in the deadtime in the incoming PWM signals and output them. I have 6 incoming PWM signals to switch 6 IGBTs. So, these 6 p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Also make sure that your simulation inputs are timed correctly with respect to the clock so that there are no setup or hold violations. This is important for a timing simulation.