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Honored Contributor
Honored ContributorSome glitches in the simualtion waveforms
Hi, Experts, I met a problem in my VHDL code. My algorithm is to cut in the deadtime in the incoming PWM signals and output them. I have 6 incoming PWM signals to switch 6 IGBTs. So, these 6 p...
Altera_ForumHonored Contributor
Honored ContributorIf you are getting the warnings below, then clean up the coding style to eliminate the warnings.
Warning (10631): VHDL Process Statement warning at deadtime_1.vhd(69): inferring latch(es) for signal or variable "start_cal", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at deadtime_1.vhd(69): inferring latch(es) for signal or variable "start_pwm", which holds its previous value in one or more paths through the process
