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I'm sorry but I still don't understand what your problem is or what you want to achieve.
The PLL needs a valid clock input. It can either be the output of another pll or one of the FPGA's pins. In your case you can pick up from the kit manual the number of the pin that is connected to an oscillator, and connect that pin to the pll's input. This seems to be what you did.
Now the PLL's outputs are connected to the FPGA's global clock network and can be directly used by your logic. It isn't related to any pin.
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Ah ok, clear now, then why in the assignement pins he appear to me the output clock, can i let then the output clock without any assignement.
For the input i related it with an oscillator as you say.
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