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Altera_Forum's avatar
Altera_Forum
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14 years ago

simulation result of "case" is one clk delayed?

totally, in the module "vnp" there are 256(parameter N=256) "cnt"s to deal with. every "cnt" should go through a "Cycle". One Cycle contains 3 steps. So the value of "Cycle" goes from 2'...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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It doesn't happen at Cycle == 1. Mess_Buff_a[0] is updated in the same clock cycle when Cycle is incremented from 0 to 1, as your code commands. This is how synchronous logic works.

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thank you very much.

I have misunderstanding the codes.

the waveforms are right.