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Honored Contributor
Honored Contributorsimulation result of "case" is one clk delayed?
totally, in the module "vnp" there are 256(parameter N=256) "cnt"s to deal with. every "cnt" should go through a "Cycle". One Cycle contains 3 steps. So the value of "Cycle" goes from 2'...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- It doesn't happen at Cycle == 1. Mess_Buff_a[0] is updated in the same clock cycle when Cycle is incremented from 0 to 1, as your code commands. This is how synchronous logic works. --- Quote End --- thank you very much. I have misunderstanding the codes. the waveforms are right.
