Simulating a VHDL array

Okay, thanks for the help. I changed the code to:

library ieee;

use ieee.std_logic_1164.all;

package pkg_array is

type vec_array is array(integer range <>) of std_logic_vector(7 downto 0);

end pkg_array;

library ieee;

use ieee.std_logic_1164.all;

use work.pkg_array.all;

entity gen_mux is

generic (n: integer := 2); -- Set the number of 8 bit inputs (2**n)

port(

x: in vec_array(0 to (2**n - 1));

sel: in integer range 0 to (2**n - 1);

y: out std_logic_vector(7 downto 0));

end gen_mux;

architecture description of gen_mux is

begin

y <= x(sel);

end description;

Here's the tcl command I used to drive the x inputs, with the resultant error:

force -freeze sim:/gen_mux/x {{{00000001} {00000111} {10101010} {11110000}}} 0# ** Error: (vsim-3455) Can force arrays only if they are one-dimensional arrays of character enums.

Is there a way to change this code so that Modelsim-Altera will allow me to drive the inputs?

Thanks,

Steve