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emma97's avatar
emma97
Icon for New Contributor rankNew Contributor
4 years ago

Simple MAX 10 project with DDR3 UniPHY using HDL only

I want to implement a simple hdl design for the Arrow DECA. Most examples make use of other IP's like the Nios II Processor to control the DDR3 SDRAM. But I want to build my IP Variation and control ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Emma97,


I'm Adzim. Thank you for using Intel Community.


Did the design passed calibration?

If yes, then I think you should use a larger burst size such as 32 or 64.


You can refer to the Table 96. Local Interface Signals on "External Memory Interface Handbook Volume 3". I think the signals have been explained there.


The avl_burstbegin indicates when the burst operation will start.

You may read this document for better understanding: https://www.intel.com/content/www/us/en/docs/programmable/683091/20-1/burst-transfers.html


Thanks,

Adzim