signed/unsigned multipliers

Thanks for your input FvM

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Signed/unsigned is a parameter rather than an input port to lpm_mult. So it can't be changed during run time. I didn't try, but I guess, that in case of a hardware multiplier, two multiplier instances and a multiplexer are inferred from your code for this reason. A software (logic cell) multiplier should be able to incorporate the signed/unsigned switch during fit.

As said, the input size should 2*9 bit. I guess, assigning the input to a 18 bit value forces the multiply operands to be positive, thus signed multiply is eliminated. Also, cause the full multiply result is 36 bit, you don't get it correctly in the signed case.

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You maybe right the lpm_mult take signess as a parameter, but that's besides the point. The RTL inferred from the above Verilog is correct as can be seen with the RTL technology viewer. Yes, it does infer two multipliers, but if you read http://www.altera.com/literature/hb/cyc2/cyc2_cii51012.pdf page 12-5, it is explicitly stated that "Two signals, signa and signb, control whether a multiplier’s input is a signed or unsigned value. ... The signa and signb signals can be changed dynamically to modify the sign representation of the input operands at run time." Furthermore, if you inspect with the post mapping technology viewer, the signa/signb signal is visible, but wired to ground - ignoring the inferred RTL.

So there are two issues

- Quartus II 8.1 fails to handle my example correctly, and

- I don't know a workaround.

Why do I care? I'm implementing a processor that has both a signed and unsigned multiplication. The workaround you both suggest would hurt performance due to the additional mux.