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Altera_Forum's avatar
Altera_Forum
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14 years ago

several questions

1: The quartusII popup a message ,that is "the design has changed,Do you wish to recompile before running the logic analyzer" ,then I recompile the project,and try to run the signaltapII logic analyzer,the message show up again, is this the bug of the software (I am sure there is no change in the quartusII project )?

then I delete the .stp file and rebuild a new one ,the message donnot show up , but I donnot want to rebuid a new ,stp file every time!!~

2: I have design a FPGA board by myself, the device is EP2C35F484, the core voltage is 1.2V ,and the VCCIO is 3.3V, when the core voltage is 1.5V and VCCIO is 3.1V ,the FPGA also can work ,so I wander what is the voltage tolerance range of them ? I did not get any information from the quartusII handbook~please help me.

thanks very much!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Q1: You should save the .stp file before compile the design.

    Q2: Refer to the cyc2 handbook for detail info.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    1: I have been saved the .sof file before compiled the quartusII project ,because the software will warn you to save all the file before compiltion.

    2: YES, I refer the cycloneII handbook ,but I have not find the voltage tolerence ,can you tell me where I can find it?

    thanks ~