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Honored Contributor
Honored Contributorsetup violation problem
Hello, I have a problem related to timing setup violation, my device is EP2C20F484C7, and I use classic timing analyzer as timing analysis tool. In addition, I use one global clock running at...
Altera_ForumHonored Contributor
Honored ContributorI did several simulations and found out that several clock paths acted as ripple or gated clocks due to some clocks generated by counter, which caused gliches and effected the timing. Thank you all for many useful ideas, I will try to modify my code.
